This application claims the priority of Korean Patent Application. No. 2003-23344, filed on Apr. 14, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a gold alloy bonding wire for electrically connecting a semiconductor chip with a leadframe or a printed circuit board (PCB) in a packaging process of a semiconductor device, and more particularly, to a gold alloy bonding wire that can be suitably used in packaging of a highly-integrated semiconductor device.
2. Description of the Related Art
As the integration density of semiconductor devices has increased and the semiconductor devices has become thinner and smaller, a distance between interconnections of a chip of an integrated circuit (IC) has become narrower. Further, current semiconductor applications require an increase in the number of pins of bonding pads and a decrease in a distance between the pins. In order to meet this requirement and enhance the reliability of a wire bonding process, an improvement in a shape of a loop of a gold alloy bonding wire, an increase in a tensile strength of the gold alloy bonding wire, an increase in resistance vibration, an increase in a bond pull strength between the gold alloy bonding wires and bonding pads after the bonding process, an increase in a ball shear strength between the gold alloy bonding wires and a leadframe, and a prevention of a chip crack, etc. are required.
In addition, as semiconductor technologies are rapidly developing, packaging technologies for ultra highly-integrated chips and multichips have been investigated and line widths of semiconductor devices and distances between bonding pads have become excessively small. Thus, ultra fining of the gold alloy bonding wire to be used in a packaging process has been required.
However, this requirement poses the following problems. First, a high-temperature reliability after ball-bonding is reduced. Secondly, ball necks of the gold alloy bonding wires in forming an ultra low loop are, damaged.
Referring to FIG. 1, a general semiconductor package includes a semiconductor chip 10 on a pad 50, a plurality of bonding pads 20, a plurality of lead frames 40, and gold (Au) alloy bonding wires 30. The plurality of bonding pads 20 are formed on the semiconductor chip 10 as input/output ports for a variety of signals. The plurality of lead frames 40 are electrically connected to the semiconductor chip 10 to receive and output the variety of signals from and to an external circuit. The Au alloy bonding wires 30 electrically connects the bonding pads 20 and the leadframes 40. The structure of the semiconductor package is encapsulated and protected by a resin, for example, epoxy molding compound.
One end of the Au alloy bonding wire 30 attached to the bonding pad 20 includes a compressed ball 32 and a neck 34 as a connector between the compressed ball 32 and the Au alloy bonding wire 30., In a wire bonding process, one end of the Au alloy bonding wire 30 is melted by discharging to form a free air ball having a predetermined size and is further pressed on the bonding pad 20 to be attached-thereto. A loop of the Au alloy bonding wire 30 having an appropriate height and length is formed to reach a corresponding leadframe 40, and the other end of the Au alloy bonding wire 30 is attached to the leadframe 40 with an application of pressure. As a result, the semiconductor chip 10 and the leadframe 40 are electrically connected.
However, when performing the bonding process using the conventional Au alloy bonding wires 30, a damage 35, such as a crack or damage, occurs frequently in the neck 34 when forming the loop of the Au alloy bonding wire 30. Particularly, as the integration density of semiconductor devices increases, the height of the loop becomes lower and the frequency of appearance of the damage 35 near the neck 34 increases. As a result, a signal transmission path through the loop is opened.